The development of a circuit and layout of the frequency meter unit for low-power integrated circuits is represented in this article. Simulation results of the device for 90 nm CMOS technology are considered. An estimation of a range of the measurable frequencies for certain values of counter stages at clock frequencies 0.25, 0.5, 1 GHz was carried out. Besides, dependences of power consumption on the frequency of the clock oscillator at the measurable frequencies from 10 MHz to 50 MHz were obtained.