In communication system encoder and decoder place an important role to detect and correct the errors. Reliability and efficiency of data transmission are the important issues in communication system. Asynchronous circuit consumes less power hence these types of circuit are used more in recent years. Low power chips having more demand in market for portable electronics devices. Electricity generation is the major source for air pollution. The using of low power chips saves power and indirectly shows the concern about environment. In this paper, efficient low power Asynchronous Viterbi decoder is designed and compares the performance parameters with the Synchronous Viterbi Decoder. The convolutional encoder is designed with the constraint length of 4 and code rate of 1/3. Viterbi Decoder having three sub modules are Branch Metric Unit(BMU), Add Compare and Select Unit, and Trace Back Unit(TBU). The Viterbi Decoder algorithm is works based on trellis diagram. Asynchronous design includes clock gating technique to reduce the power consumption. The two designs are designed using Verilog HDL and Simulated using Xilinx 13.1 ISE and implemented on FPGA. The above designs are synthesized using RTL Compiler by generating vcd file.