The pipelined accumulator forms the basic building block of arithmetic modules for DSP applications. The basic building block of an accumulator unit is the adder cell and data storage registers e.g. Flip-Flop (FF). The operational speed of FF determines the correctness and accuracy of the functionality of 12BDA. The high-speed full adders that use low power consumption is a fundamental arithmetic operation that can never be neglected in accumulator unit, and it is one of the speed-limiting elements. The efficiency of the accumulator unit is determined by the adder cell taken in to account.In this paper, a 12-Bit pipelined accumulator cell optimized for low power and high speed operation are proposed. Update rates of 150MHz are achieved by careful choice of architecture. The static, D-type flip flops used in the pipeline architecture are the dominant source of power dissipation. Hence the refresh-every-cycle operation of accumulators is exploited by using dynamic delay elements to reduce power consumption The accumulator unit is simulated with mentor graphics using the 130nm CMOS technology at different supply voltages ranges. Various metrics such as delay, static and dynamic power are simulated and reported for both pipelined and non-pipelined accumulator unit for different adder topologies.