In this brief, the logic operations involved in conventional Carry Select Adder (CSLA) and binary to excess-1 converter (BEC)-based Carry Select Adder (CSLA) are analyzed to study the data dependence and to identify redundant logic operations. We have eliminated all the redundant logic operations present in the conventional Carry Select Adder, BEC-based Carry Select Adder and proposed a new logic formulation for Carry Select Adder. In this paper a new architectures for carry select adder using AOI based logic and optimized logic expressions based structure is proposed. A simple approach is proposed using AOI logic to reduce the area, delay and power of Square root (SQRT) Carry Select Adder architecture. The reduced number of gates of this work offers the great advantage in the reduction of area and also the total power. Due to the optimized area, power and delay, the proposed Carry Select Adder design is a good substitution for all the existing Carry Select Adder. The proposed architecture is designed using Verilog HDL (Hardware Description Language) and is then synthesized using XILINX 14.5and is simulated in ISim for Spartan 3E FPGA.