In Integrated circuits a giant portion of chip power is spent by duration system that contains of temporal order components like flip-flops, latches and clock distribution network. This paper enumerates power economical style of shift registers mistreatment D flip-flops together with Clock and Power gating integration. Clock gating and power gating proves to be terribly effective solutions for reducing dynamic and active outpouring power severally. The 2 techniques square measure coupled in such the simplest way that the clock gating data is employed to drive the management signal of power-gating electronic equipment. During this paper, AN activity driven fine-grained clock and power gating is projected. First, a method named Optimized Bus-Specific-Clock-Gating (OBSC) is introduced that reduces the matter of gated flip-flop choice by applicable choice of set of flip-flops. Then another technique named Run Time Power Gating (RTPG) is projected for power gating the combinatory logics activity redundant operations. The projected shift registers square measure designed up to the layout level with 1V Power provide in zero.18um technology and simulated mistreatment Tanner Tools.