Testing in VLSI circuit is difficult due to the many challenges as a rapid growth in design complexity. These challenges include the power dissipation and test application time within particular limit of time. Actually in basic LFSR power consumption is high. This paper is proposed method to existing Bit Swapping and Low Power Linear Feedback Shift Register. This paper explains the Automatic test pattern generation on Built in Self Test. In ordinary LFSR the random test vectors can be generated but the power consumption is high because of more number of transitions. The modified LFSR's are BS-LFSR and LP-LFSR. To overcome this ordinary LFSR disadvantage the existing LP-LFSR and BS-LFSR are used. Here we are using twisted ring counter and level generator.TPS and TPC are implemented using these. Here we are using the benchmark circuit , C432 as a DUT. Here, both TPC and TPS are done by using LFSR ,BS-LFSR and LP-LFSR. TPS with LP-LFSR and BS-LFSR is lower than the power during TPC. The power calculation is done in modelsim. This results show power reduced in respectively with different methods.