The Adders are the critical elements in most of the digital circuit designs, including digital signal processors (DSP) and microprocessors. Extensive research has gone into the VLSI implementations of Parallel Prefix Adders which are known for their best performance.

The performance of Parallel Prefix Adders is directly affected by the constraints in the logic implementations of Parallel Prefix Adders in FPGA. This paper investigates the delay performance of three types of Carry Tree Adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and compares them with the simple Ripple Carry Adder (RCA) and Carry Skip Adder (CSA). These designs of varied bit-widths were implemented on a Xilinx Spartan 3E FPGA and delay measurements were made with a high-performance logic analyzer. Due to the presence of a fast carry-chain, the RCA designs exhibit better delay performance up to 128 bits. The carry-tree adders are expected to have a speed advantage over the RCA as bit widths approach 256.

This comparison study is done using Modelsim for logical verification. Synthesizing was done using Xilinx-ISE tool.